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board_hw_defs.c
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1 
12 /*
13  * This program is free software; you can redistribute it and/or modify
14  * it under the terms of the GNU General Public License as published by
15  * the Free Software Foundation; either version 3 of the License, or
16  * (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful, but
19  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
20  * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
21  * for more details.
22  *
23  * You should have received a copy of the GNU General Public License along
24  * with this program; if not, see <http://www.gnu.org/licenses/>
25  *
26  * Additional note on redistribution: The copyright and license notices above
27  * must be maintained in each individual source file that is a derivative work
28  * of this source file; otherwise redistribution is prohibited.
29  */
30 
31 #include <pios_config.h>
32 #include <pios_board_info.h>
33 
34 #if defined(PIOS_INCLUDE_ANNUNC)
35 
36 #include <pios_annunc_priv.h>
37 
38 static const struct pios_annunc pios_annuncs[] = {
39  [PIOS_LED_HEARTBEAT] = {
40  .pin = {
41  .gpio = GPIOC,
42  .init = {
43  .GPIO_Pin = GPIO_Pin_4,
44  .GPIO_Speed = GPIO_Speed_50MHz,
45  .GPIO_Mode = GPIO_Mode_OUT,
46  .GPIO_OType = GPIO_OType_PP,
47  .GPIO_PuPd = GPIO_PuPd_UP
48  },
49  },
50  },
51  [PIOS_LED_ALARM] = {
52  .pin = {
53  .gpio = GPIOC,
54  .init = {
55  .GPIO_Pin = GPIO_Pin_5,
56  .GPIO_Speed = GPIO_Speed_50MHz,
57  .GPIO_Mode = GPIO_Mode_OUT,
58  .GPIO_OType = GPIO_OType_PP,
59  .GPIO_PuPd = GPIO_PuPd_UP
60  },
61  },
62  },
63 };
64 
65 static const struct pios_annunc_cfg pios_annunc_cfg = {
66  .annunciators = pios_annuncs,
67  .num_annunciators = NELEMENTS(pios_annuncs),
68 };
69 
70 const struct pios_annunc_cfg * PIOS_BOARD_HW_DEFS_GetLedCfg (uint32_t board_revision)
71 {
72  (void)board_revision;
73  return &pios_annunc_cfg;
74 }
75 
76 #endif /* PIOS_INCLUDE_ANNUNC */
77 
78 
79 #if defined(PIOS_INCLUDE_FLASH)
81 
82 static const struct flashfs_logfs_cfg flashfs_settings_internal_cfg = {
83  .fs_magic = 0x99abcedf,
84  .arena_size = 0x00004000, /* 256 * slot size */
85  .slot_size = 0x00000100, /* 256 bytes */
86 };
87 
88 #if defined(PIOS_INCLUDE_FLASH_INTERNAL)
90 
91 static const struct pios_flash_internal_cfg flash_internal_cfg = {
92 };
93 #endif /* PIOS_INCLUDE_FLASH_INTERNAL */
94 
95 #include "pios_flash_priv.h"
96 
97 #if defined(PIOS_INCLUDE_FLASH_INTERNAL)
98 static const struct pios_flash_sector_range stm32f4_sectors[] = {
99  {
100  .base_sector = 0,
101  .last_sector = 3,
102  .sector_size = FLASH_SECTOR_16KB,
103  },
104  {
105  .base_sector = 4,
106  .last_sector = 4,
107  .sector_size = FLASH_SECTOR_64KB,
108  },
109  {
110  .base_sector = 5,
111  .last_sector = 11,
112  .sector_size = FLASH_SECTOR_128KB,
113  },
114 
115 };
116 
117 uintptr_t pios_internal_flash_id;
118 static const struct pios_flash_chip pios_flash_chip_internal = {
120  .chip_id = &pios_internal_flash_id,
121  .page_size = 16, /* 128-bit rows */
122  .sector_blocks = stm32f4_sectors,
123  .num_blocks = NELEMENTS(stm32f4_sectors),
124 };
125 #endif /* PIOS_INCLUDE_FLASH_INTERNAL */
126 
127 static const struct pios_flash_partition pios_flash_partition_table_internal[] = {
128 #if defined(PIOS_INCLUDE_FLASH_INTERNAL)
129  {
131  .chip_desc = &pios_flash_chip_internal,
132  .first_sector = 0,
133  .last_sector = 1,
134  .chip_offset = 0,
135  .size = (1 - 0 + 1) * FLASH_SECTOR_16KB,
136  },
137 
138  {
140  .chip_desc = &pios_flash_chip_internal,
141  .first_sector = 2,
142  .last_sector = 3,
143  .chip_offset = (2 * FLASH_SECTOR_16KB),
144  .size = (3 - 2 + 1) * FLASH_SECTOR_16KB,
145  },
146 
147  {
148  .label = FLASH_PARTITION_LABEL_FW,
149  .chip_desc = &pios_flash_chip_internal,
150  .first_sector = 5,
151  .last_sector = 7,
152  .chip_offset = (4 * FLASH_SECTOR_16KB) + (1 * FLASH_SECTOR_64KB),
153  .size = (7 - 5 + 1) * FLASH_SECTOR_128KB,
154  },
155 
156  /* NOTE: sectors 8-11 of the internal flash are currently unallocated */
157 
158 #endif /* PIOS_INCLUDE_FLASH_INTERNAL */
159 };
160 
162 const struct pios_flash_partition *PIOS_BOARD_HW_DEFS_GetPartitionTable (uint32_t board_revision, uint32_t *num_partitions)
163 {
164  (void)board_revision;
165  PIOS_Assert(num_partitions);
166  *num_partitions = NELEMENTS(pios_flash_partition_table_internal);
167  return pios_flash_partition_table_internal;
168 }
169 
170 #endif /* PIOS_INCLUDE_FLASH */
171 
172 #include <pios_usart_priv.h>
173 
174 /*
175  * MAIN USART
176  */
177 static const struct pios_usart_cfg pios_usart_main_cfg = {
178  .regs = USART3,
179  .remap = GPIO_AF_USART3,
180  .irq = {
181  .init = {
182  .NVIC_IRQChannel = USART3_IRQn,
183  .NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_MID,
184  .NVIC_IRQChannelSubPriority = 0,
185  .NVIC_IRQChannelCmd = ENABLE,
186  },
187  },
188  .rx = {
189  .gpio = GPIOB,
190  .init = {
191  .GPIO_Pin = GPIO_Pin_11,
192  .GPIO_Speed = GPIO_Speed_2MHz,
193  .GPIO_Mode = GPIO_Mode_AF,
194  .GPIO_OType = GPIO_OType_PP,
195  .GPIO_PuPd = GPIO_PuPd_UP
196  },
197  },
198  .tx = {
199  .gpio = GPIOB,
200  .init = {
201  .GPIO_Pin = GPIO_Pin_10,
202  .GPIO_Speed = GPIO_Speed_2MHz,
203  .GPIO_Mode = GPIO_Mode_AF,
204  .GPIO_OType = GPIO_OType_PP,
205  .GPIO_PuPd = GPIO_PuPd_UP
206  },
207  },
208 };
209 
210 #if defined(PIOS_INCLUDE_COM)
211 
212 #include <pios_com_priv.h>
213 
214 #endif /* PIOS_INCLUDE_COM */
215 
216 
217 #if defined(PIOS_INCLUDE_RTC)
218 /*
219  * Realtime Clock (RTC)
220  */
221 #include <pios_rtc_priv.h>
222 
223 void PIOS_RTC_IRQ_Handler (void);
224 void RTC_WKUP_IRQHandler() __attribute__ ((alias ("PIOS_RTC_IRQ_Handler")));
225 static const struct pios_rtc_cfg pios_rtc_main_cfg = {
226  .clksrc = RCC_RTCCLKSource_HSE_Div8, // Divide 8 Mhz crystal down to 1
227  // This clock is then divided by another 16 to give a nominal 62.5 khz clock
228  .prescaler = 100, // Every 100 cycles gives 625 Hz
229  .irq = {
230  .init = {
231  .NVIC_IRQChannel = RTC_WKUP_IRQn,
232  .NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_MID,
233  .NVIC_IRQChannelSubPriority = 0,
234  .NVIC_IRQChannelCmd = ENABLE,
235  },
236  },
237 };
238 
239 void PIOS_RTC_IRQ_Handler (void)
240 {
242 }
243 
244 #endif
245 
246 #include "pios_tim_priv.h"
247 
248 // Set up timers on APB1
249 // TIM2,3,4,5,6,7,12,13,14
250 static const TIM_TimeBaseInitTypeDef tim_apb1_time_base = {
251  .TIM_Prescaler = (PIOS_PERIPHERAL_APB1_COUNTER_CLOCK / 1000000) - 1,
252  .TIM_ClockDivision = TIM_CKD_DIV1,
253  .TIM_CounterMode = TIM_CounterMode_Up,
254  .TIM_Period = 0xFFFF,
255  .TIM_RepetitionCounter = 0x0000,
256 };
257 
258 
259 // Set up timers on APB2
260 // TIM1,8,9,10,11
261 static const TIM_TimeBaseInitTypeDef tim_apb2_time_base = {
262  .TIM_Prescaler = (PIOS_PERIPHERAL_APB2_COUNTER_CLOCK / 1000000) - 1,
263  .TIM_ClockDivision = TIM_CKD_DIV1,
264  .TIM_CounterMode = TIM_CounterMode_Up,
265  .TIM_Period = 0xFFFF,
266  .TIM_RepetitionCounter = 0x0000,
267 };
268 
269 
270 static const struct pios_tim_clock_cfg tim_3_cfg = {
271  .timer = TIM3,
272  .time_base_init = &tim_apb1_time_base,
273  .irq = {
274  .init = {
275  .NVIC_IRQChannel = TIM3_IRQn,
276  .NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_MID,
277  .NVIC_IRQChannelSubPriority = 0,
278  .NVIC_IRQChannelCmd = ENABLE,
279  },
280  },
281 };
282 
283 static const struct pios_tim_clock_cfg tim_5_cfg = {
284  .timer = TIM5,
285  .time_base_init = &tim_apb1_time_base,
286  .irq = {
287  .init = {
288  .NVIC_IRQChannel = TIM5_IRQn,
289  .NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_MID,
290  .NVIC_IRQChannelSubPriority = 0,
291  .NVIC_IRQChannelCmd = ENABLE,
292  },
293  },
294 };
295 
296 static const struct pios_tim_clock_cfg tim_8_cfg = {
297  .timer = TIM8,
298  .time_base_init = &tim_apb2_time_base,
299  .irq = {
300  .init = {
301  .NVIC_IRQChannel = TIM8_CC_IRQn,
302  .NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_MID,
303  .NVIC_IRQChannelSubPriority = 0,
304  .NVIC_IRQChannelCmd = ENABLE,
305  },
306  },
307 };
308 
309 static const struct pios_tim_clock_cfg tim_9_cfg = {
310  .timer = TIM9,
311  .time_base_init = &tim_apb2_time_base,
312  .irq = {
313  .init = {
314  .NVIC_IRQChannel = TIM1_BRK_TIM9_IRQn,
315  .NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_MID,
316  .NVIC_IRQChannelSubPriority = 0,
317  .NVIC_IRQChannelCmd = ENABLE,
318  },
319  },
320 };
321 
322 static const struct pios_tim_clock_cfg tim_12_cfg = {
323  .timer = TIM12,
324  .time_base_init = &tim_apb1_time_base,
325  .irq = {
326  .init = {
327  .NVIC_IRQChannel = TIM8_BRK_TIM12_IRQn,
328  .NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_MID,
329  .NVIC_IRQChannelSubPriority = 0,
330  .NVIC_IRQChannelCmd = ENABLE,
331  },
332  },
333 };
334 
335 
336 #if defined(PIOS_INCLUDE_USB)
337 #include "pios_usb_priv.h"
338 
339 static const struct pios_usb_cfg pios_usb_main_cfg = {
340  .irq = {
341  .init = {
342  .NVIC_IRQChannel = OTG_FS_IRQn,
343  .NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_HIGHEST,
344  .NVIC_IRQChannelSubPriority = 3,
345  .NVIC_IRQChannelCmd = ENABLE,
346  },
347  },
348 };
349 
350 const struct pios_usb_cfg *PIOS_BOARD_HW_DEFS_GetUsbCfg (uint32_t board_revision)
351 {
352  (void)board_revision;
353  return &pios_usb_main_cfg;
354 }
355 
359 #include "pios_usbhook.h"
360 
361 #endif /* PIOS_INCLUDE_USB */
362 
363 #if defined(PIOS_INCLUDE_COM_MSG)
364 
365 #include <pios_com_msg_priv.h>
366 
367 #endif /* PIOS_INCLUDE_COM_MSG */
368 
369 #if defined(PIOS_INCLUDE_USB_HID) && !defined(PIOS_INCLUDE_USB_CDC)
370 #include <pios_usb_hid_priv.h>
371 
372 const struct pios_usb_hid_cfg pios_usb_hid_cfg = {
373  .data_if = 0,
374  .data_rx_ep = 1,
375  .data_tx_ep = 1,
376 };
377 #endif /* PIOS_INCLUDE_USB_HID && !PIOS_INCLUDE_USB_CDC */
378 
379 #if defined(PIOS_INCLUDE_USB_HID) && defined(PIOS_INCLUDE_USB_CDC)
380 #include <pios_usb_cdc_priv.h>
381 
382 const struct pios_usb_cdc_cfg pios_usb_cdc_cfg = {
383  .ctrl_if = 0,
384  .ctrl_tx_ep = 2,
385 
386  .data_if = 1,
387  .data_rx_ep = 3,
388  .data_tx_ep = 3,
389 };
390 
391 #include <pios_usb_hid_priv.h>
392 
393 const struct pios_usb_hid_cfg pios_usb_hid_cfg = {
394  .data_if = 2,
395  .data_rx_ep = 1,
396  .data_tx_ep = 1,
397 };
398 #endif /* PIOS_INCLUDE_USB_HID && PIOS_INCLUDE_USB_CDC */
399 
400 
401 #if defined(PIOS_INCLUDE_CAN)
402 #include "pios_can_priv.h"
403 struct pios_can_cfg pios_can_cfg = {
404  .regs = CAN1,
405  .init = {
406  // To make it easy to use both F3 and F4 use the other APB1 bus rate
407  // divided by 2. This matches the baud rate across devices
408  .CAN_Prescaler = 21-1,
410  .CAN_Mode = CAN_Mode_Normal,
412  .CAN_SJW = CAN_SJW_1tq,
416  .CAN_BS1 = CAN_BS1_9tq,
419  .CAN_BS2 = CAN_BS2_8tq,
421  .CAN_TTCM = DISABLE,
423  .CAN_ABOM = DISABLE,
425  .CAN_AWUM = DISABLE,
427  .CAN_NART = ENABLE,
429  .CAN_RFLM = DISABLE,
431  .CAN_TXFP = DISABLE,
433  },
434  .remap = GPIO_AF_CAN1,
435  .tx = {
436  .gpio = GPIOB,
437  .init = {
438  .GPIO_Pin = GPIO_Pin_9,
439  .GPIO_Speed = GPIO_Speed_50MHz,
440  .GPIO_Mode = GPIO_Mode_AF,
441  .GPIO_OType = GPIO_OType_PP,
442  .GPIO_PuPd = GPIO_PuPd_UP
443  },
444  .pin_source = GPIO_PinSource9,
445  },
446  .rx = {
447  .gpio = GPIOB,
448  .init = {
449  .GPIO_Pin = GPIO_Pin_8,
450  .GPIO_Speed = GPIO_Speed_50MHz,
451  .GPIO_Mode = GPIO_Mode_AF,
452  .GPIO_OType = GPIO_OType_PP,
453  .GPIO_PuPd = GPIO_PuPd_UP
454  },
455  .pin_source = GPIO_PinSource8,
456  },
457  .rx_irq = {
458  .init = {
459  .NVIC_IRQChannel = CAN1_RX1_IRQn,
460  .NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_MID,
461  .NVIC_IRQChannelSubPriority = 0,
462  .NVIC_IRQChannelCmd = ENABLE,
463  },
464  },
465  .tx_irq = {
466  .init = {
467  .NVIC_IRQChannel = CAN1_TX_IRQn,
468  .NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_MID,
469  .NVIC_IRQChannelSubPriority = 0,
470  .NVIC_IRQChannelCmd = ENABLE,
471  },
472  },
473 };
474 
475 #endif /* PIOS_INCLUDE_CAN */
476 
477 #if defined(PIOS_INCLUDE_VIDEO)
478 #include <pios_video.h>
479 
480 void set_bw_levels(uint8_t black, uint8_t white)
481 {
482  TIM1->CCR1 = black;
483  TIM1->CCR3 = white;
484 }
485 
486 static const struct pios_exti_cfg pios_exti_vsync_cfg __exti_config = {
487  .vector = PIOS_Vsync_ISR,
488  .line = EXTI_Line1,
489  .pin = {
490  .gpio = GPIOB,
491  .init = {
492  .GPIO_Pin = GPIO_Pin_1,
493  .GPIO_Speed = GPIO_Speed_100MHz,
494  .GPIO_Mode = GPIO_Mode_IN,
495  .GPIO_OType = GPIO_OType_OD,
496  .GPIO_PuPd = GPIO_PuPd_NOPULL,
497  },
498  },
499  .irq = {
500  .init = {
501  .NVIC_IRQChannel = EXTI1_IRQn,
502  .NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_HIGHEST,
503  .NVIC_IRQChannelSubPriority = 0,
504  .NVIC_IRQChannelCmd = ENABLE,
505  },
506  },
507  .exti = {
508  .init = {
509  .EXTI_Line = EXTI_Line1, // matches above GPIO pin
510  .EXTI_Mode = EXTI_Mode_Interrupt,
511  .EXTI_Trigger = EXTI_Trigger_Falling,
512  .EXTI_LineCmd = ENABLE,
513  },
514  },
515 };
516 
517 const struct pios_video_cfg pios_video_cfg = {
518  .mask_dma = DMA2,
519  .mask = {
520  .regs = SPI1,
521  .remap = GPIO_AF_SPI1,
522  .init = {
523  .SPI_Mode = SPI_Mode_Slave,
524  .SPI_Direction = SPI_Direction_1Line_Tx,
525  .SPI_DataSize = SPI_DataSize_8b,
526  .SPI_NSS = SPI_NSS_Soft,
527  .SPI_FirstBit = SPI_FirstBit_MSB,
528  .SPI_CRCPolynomial = 7,
529  .SPI_CPOL = SPI_CPOL_Low,
530  .SPI_CPHA = SPI_CPHA_2Edge,
531  .SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2,
532  },
533  .dma = {
534  .irq = {
535  .flags = (DMA_IT_TCIF3),
536  .init = {
537  .NVIC_IRQChannel = DMA2_Stream3_IRQn,
538  .NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_HIGHEST,
539  .NVIC_IRQChannelSubPriority = 0,
540  .NVIC_IRQChannelCmd = ENABLE,
541  },
542  },
543  /*.rx = {},*/
544  .tx = {
545  .channel = DMA2_Stream3,
546  .init = {
547  .DMA_Channel = DMA_Channel_3,
548  .DMA_PeripheralBaseAddr = (uint32_t)&(SPI1->DR),
549  .DMA_DIR = DMA_DIR_MemoryToPeripheral,
550  .DMA_BufferSize = BUFFER_WIDTH,
551  .DMA_PeripheralInc = DMA_PeripheralInc_Disable,
552  .DMA_MemoryInc = DMA_MemoryInc_Enable,
553  .DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte,
554  .DMA_MemoryDataSize = DMA_MemoryDataSize_Word,
555  .DMA_Mode = DMA_Mode_Normal,
556  .DMA_Priority = DMA_Priority_VeryHigh,
557  .DMA_FIFOMode = DMA_FIFOMode_Enable,
558  .DMA_FIFOThreshold = DMA_FIFOThreshold_Full,
559  .DMA_MemoryBurst = DMA_MemoryBurst_INC4,
560  .DMA_PeripheralBurst = DMA_PeripheralBurst_Single,
561  },
562  },
563  },
564  .sclk = {
565  .gpio = GPIOA,
566  .init = {
567  .GPIO_Pin = GPIO_Pin_5,
568  .GPIO_Speed = GPIO_Speed_100MHz,
569  .GPIO_Mode = GPIO_Mode_AF,
570  .GPIO_OType = GPIO_OType_PP,
571  .GPIO_PuPd = GPIO_PuPd_NOPULL
572  },
573  },
574  .miso = {
575  .gpio = GPIOA,
576  .init = {
577  .GPIO_Pin = GPIO_Pin_6,
578  .GPIO_Speed = GPIO_Speed_50MHz,
579  .GPIO_Mode = GPIO_Mode_AF,
580  .GPIO_OType = GPIO_OType_PP,
581  .GPIO_PuPd = GPIO_PuPd_NOPULL
582  },
583  },
584  .slave_count = 1,
585  },
586  .level_dma = DMA1,
587  .level = {
588  .regs = SPI2,
589  .remap = GPIO_AF_SPI2,
590  .init = {
591  .SPI_Mode = SPI_Mode_Slave,
592  .SPI_Direction = SPI_Direction_1Line_Tx,
593  .SPI_DataSize = SPI_DataSize_8b,
594  .SPI_NSS = SPI_NSS_Soft,
595  .SPI_FirstBit = SPI_FirstBit_MSB,
596  .SPI_CRCPolynomial = 7,
597  .SPI_CPOL = SPI_CPOL_Low,
598  .SPI_CPHA = SPI_CPHA_2Edge,
599  .SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2,
600  },
601  .dma = {
602  .irq = {
603  .flags = (DMA_IT_TCIF4),
604  .init = {
605  .NVIC_IRQChannel = DMA1_Stream4_IRQn,
606  .NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_HIGHEST,
607  .NVIC_IRQChannelSubPriority = 0,
608  .NVIC_IRQChannelCmd = ENABLE,
609  },
610  },
611  /*.rx = {},*/
612  .tx = {
613  .channel = DMA1_Stream4,
614  .init = {
615  .DMA_Channel = DMA_Channel_0,
616  .DMA_PeripheralBaseAddr = (uint32_t)&(SPI2->DR),
617  .DMA_DIR = DMA_DIR_MemoryToPeripheral,
618  .DMA_BufferSize = BUFFER_WIDTH,
619  .DMA_PeripheralInc = DMA_PeripheralInc_Disable,
620  .DMA_MemoryInc = DMA_MemoryInc_Enable,
621  .DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte,
622  .DMA_MemoryDataSize = DMA_MemoryDataSize_Word,
623  .DMA_Mode = DMA_Mode_Normal,
624  .DMA_Priority = DMA_Priority_VeryHigh,
625  .DMA_FIFOMode = DMA_FIFOMode_Enable,
626  .DMA_FIFOThreshold = DMA_FIFOThreshold_Full,
627  .DMA_MemoryBurst = DMA_MemoryBurst_INC4,
628  .DMA_PeripheralBurst = DMA_PeripheralBurst_Single,
629  },
630  },
631  },
632  .sclk = {
633  .gpio = GPIOB,
634  .init = {
635  .GPIO_Pin = GPIO_Pin_13,
636  .GPIO_Speed = GPIO_Speed_100MHz,
637  .GPIO_Mode = GPIO_Mode_AF,
638  .GPIO_OType = GPIO_OType_PP,
639  .GPIO_PuPd = GPIO_PuPd_UP
640  },
641  },
642  .miso = {
643  .gpio = GPIOC,
644  .init = {
645  .GPIO_Pin = GPIO_Pin_2,
646  .GPIO_Speed = GPIO_Speed_50MHz,
647  .GPIO_Mode = GPIO_Mode_AF,
648  .GPIO_OType = GPIO_OType_PP,
649  .GPIO_PuPd = GPIO_PuPd_UP
650  },
651  },
652  .slave_count = 1,
653  },
654 
655  .vsync = &pios_exti_vsync_cfg,
656 
657  .hsync_capture = {
658  .timer = TIM2,
659  .timer_chan = TIM_Channel_2,
660  .pin = {
661  .gpio = GPIOB,
662  .init = {
663  .GPIO_Pin = GPIO_Pin_3,
664  .GPIO_Speed = GPIO_Speed_100MHz,
665  .GPIO_Mode = GPIO_Mode_AF,
666  .GPIO_OType = GPIO_OType_PP,
667  .GPIO_PuPd = GPIO_PuPd_UP
668  },
669  .pin_source = GPIO_PinSource3,
670  },
671  .remap = GPIO_AF_TIM2,
672  },
673 
674  .pixel_timer = {
675  .timer = TIM3,
676  .timer_chan = TIM_Channel_1,
677  .pin = {
678  .gpio = GPIOB,
679  .init = {
680  .GPIO_Pin = GPIO_Pin_4,
681  .GPIO_Speed = GPIO_Speed_100MHz,
682  .GPIO_Mode = GPIO_Mode_AF,
683  .GPIO_OType = GPIO_OType_PP,
684  .GPIO_PuPd = GPIO_PuPd_UP
685  },
686  .pin_source = GPIO_PinSource4,
687  },
688  .remap = GPIO_AF_TIM3,
689  },
690 
691  .tim_oc_init = {
692  .TIM_OCMode = TIM_OCMode_PWM1,
693  .TIM_OutputState = TIM_OutputState_Enable,
694  .TIM_OutputNState = TIM_OutputNState_Disable,
695  .TIM_Pulse = 1,
696  .TIM_OCPolarity = TIM_OCPolarity_High,
697  .TIM_OCNPolarity = TIM_OCPolarity_High,
698  .TIM_OCIdleState = TIM_OCIdleState_Reset,
699  .TIM_OCNIdleState = TIM_OCNIdleState_Reset,
700  },
701  .set_bw_levels = set_bw_levels,
702 };
703 
704 #endif /* if defined(PIOS_INCLUDE_VIDEO) */
705 
706 #if defined(PIOS_INCLUDE_SPI)
707 #include <pios_spi_priv.h>
708 
709 /*
710  * SPI3 Interface
711  * Used for MAX7456
712  */
713 static const struct pios_spi_cfg pios_spi_max7456_cfg = {
714  .regs = SPI3,
715  .remap = GPIO_AF_SPI3,
716  .init = {
717  .SPI_Mode = SPI_Mode_Master,
718  .SPI_Direction = SPI_Direction_2Lines_FullDuplex,
719  .SPI_DataSize = SPI_DataSize_8b,
720  .SPI_NSS = SPI_NSS_Soft,
721  .SPI_FirstBit = SPI_FirstBit_MSB,
722  .SPI_CRCPolynomial = 7,
723  .SPI_CPOL = SPI_CPOL_Low,
724  .SPI_CPHA = SPI_CPHA_1Edge,
725  .SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_8,
726  },
727  .sclk = {
728  .gpio = GPIOC,
729  .init = {
730  .GPIO_Pin = GPIO_Pin_10,
731  .GPIO_Speed = GPIO_Speed_100MHz,
732  .GPIO_Mode = GPIO_Mode_AF,
733  .GPIO_OType = GPIO_OType_PP,
734  .GPIO_PuPd = GPIO_PuPd_NOPULL
735  },
736  },
737  .miso = {
738  .gpio = GPIOC,
739  .init = {
740  .GPIO_Pin = GPIO_Pin_11,
741  .GPIO_Speed = GPIO_Speed_50MHz,
742  .GPIO_Mode = GPIO_Mode_AF,
743  .GPIO_OType = GPIO_OType_PP,
744  .GPIO_PuPd = GPIO_PuPd_NOPULL
745  },
746  },
747  .mosi = {
748  .gpio = GPIOC,
749  .init = {
750  .GPIO_Pin = GPIO_Pin_12,
751  .GPIO_Speed = GPIO_Speed_50MHz,
752  .GPIO_Mode = GPIO_Mode_AF,
753  .GPIO_OType = GPIO_OType_PP,
754  .GPIO_PuPd = GPIO_PuPd_NOPULL
755  },
756  },
757  .slave_count = 1,
758  .ssel = {
759  { // MAX7456
760  .gpio = GPIOA,
761  .init = {
762  .GPIO_Pin = GPIO_Pin_15,
763  .GPIO_Speed = GPIO_Speed_50MHz,
764  .GPIO_Mode = GPIO_Mode_OUT,
765  .GPIO_OType = GPIO_OType_PP,
766  .GPIO_PuPd = GPIO_PuPd_UP
767  }
768  },
769  },
770 };
771 
772 pios_spi_t pios_spi_max7456_id;
773 
774 #endif // defined(PIOS_INCLUDE_SPI)
775 
static const struct pios_tim_clock_cfg tim_12_cfg
struct stm32_gpio pin
static const struct pios_tim_clock_cfg tim_3_cfg
CAN_TypeDef * regs
Definition: pios_can_priv.h:36
static const TIM_TimeBaseInitTypeDef tim_apb2_time_base
SPI private definitions.
#define NELEMENTS(x)
Definition: pios.h:192
OSD gen module, handles OSD draw. Parts from CL-OSD and SUPEROSD projects.
COM private definitions.
COM MSG private definitions.
APIs for PIOS_USBHOOK layer.
GPIO_TypeDef * gpio
Definition: pios_stm32.h:60
void(* set_bw_levels)(uint8_t, uint8_t)
Definition: pios_video.h:104
static const struct pios_usart_cfg pios_usart_main_cfg
#define PIOS_IRQ_PRIO_HIGHEST
Definition: pios_board.h:172
PiOS CAN interface header.
Defines the API to set up the HID + CDC USB descriptor config.
static const struct pios_tim_clock_cfg tim_8_cfg
#define RTC_WKUP_IRQHandler
#define PIOS_LED_ALARM
Definition: pios_board.h:86
#define PIOS_IRQ_PRIO_MID
Definition: pios_board.h:170
USART private definitions.
#define FLASH_SECTOR_64KB
static const TIM_TimeBaseInitTypeDef tim_apb1_time_base
TIM_TypeDef * timer
Definition: pios_tim_priv.h:7
SPI_TypeDef * regs
Definition: pios_spi_priv.h:44
static const struct pios_tim_clock_cfg tim_5_cfg
const struct pios_annunc * annunciators
NVIC_InitTypeDef init
Definition: pios_stm32.h:36
USART_TypeDef * regs
USB private definitions.
USB COM HID private definitions.
#define FLASH_SECTOR_16KB
DMA_TypeDef * mask_dma
Definition: pios_video.h:96
Defines the API to set up the HID-only USB descriptor config.
void PIOS_RTC_irq_handler(void)
const struct pios_flash_driver * driver
#define BUFFER_WIDTH
Definition: pios_video.h:147
bool PIOS_Vsync_ISR()
static const struct pios_tim_clock_cfg tim_9_cfg
USB COM CDC private definitions.
uint32_t clksrc
Definition: pios_rtc_priv.h:37
enum pios_flash_partition_labels label
board_revision
Definition: board_hw_defs.c:35
#define PIOS_Assert(test)
Definition: pios_debug.h:52
LED private definitions.
struct stm32_irq irq
Definition: pios_usb_priv.h:37
#define FLASH_SECTOR_128KB
const struct pios_flash_driver pios_internal_flash_driver
#define PIOS_LED_HEARTBEAT
Definition: pios_board.h:85
#define __exti_config
Definition: pios_exti.h:48
Defines the API to the board-specific USB data setup code.