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#define | STM32F4xx_MCUCONF |
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#define | STM32_NO_INIT FALSE |
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#define | STM32_HSI_ENABLED TRUE |
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#define | STM32_LSI_ENABLED TRUE |
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#define | STM32_HSE_ENABLED TRUE |
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#define | STM32_LSE_ENABLED FALSE |
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#define | STM32_CLOCK48_REQUIRED TRUE |
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#define | STM32_SW STM32_SW_PLL |
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#define | STM32_PLLSRC STM32_PLLSRC_HSE |
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#define | STM32_HPRE STM32_HPRE_DIV1 |
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#define | STM32_PPRE1 STM32_PPRE1_DIV4 |
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#define | STM32_PPRE2 STM32_PPRE2_DIV2 |
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#define | STM32_RTCSEL STM32_RTCSEL_LSI |
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#define | STM32_RTCPRE_VALUE 8 |
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#define | STM32_MCO1SEL STM32_MCO1SEL_HSI |
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#define | STM32_MCO1PRE STM32_MCO1PRE_DIV1 |
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#define | STM32_MCO2SEL STM32_MCO2SEL_SYSCLK |
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#define | STM32_MCO2PRE STM32_MCO2PRE_DIV5 |
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#define | STM32_I2SSRC STM32_I2SSRC_CKIN |
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#define | STM32_PLLI2SN_VALUE 192 |
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#define | STM32_PLLI2SR_VALUE 5 |
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#define | STM32_PVD_ENABLE FALSE |
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#define | STM32_PLS STM32_PLS_LEV0 |
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#define | STM32_BKPRAM_ENABLE FALSE |
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#define | STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 |
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#define | STM32_ADC_USE_ADC1 FALSE |
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#define | STM32_ADC_USE_ADC2 FALSE |
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#define | STM32_ADC_USE_ADC3 FALSE |
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#define | STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) |
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#define | STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) |
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#define | STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) |
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#define | STM32_ADC_ADC1_DMA_PRIORITY 2 |
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#define | STM32_ADC_ADC2_DMA_PRIORITY 2 |
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#define | STM32_ADC_ADC3_DMA_PRIORITY 2 |
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#define | STM32_ADC_IRQ_PRIORITY 6 |
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#define | STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 |
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#define | STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 |
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#define | STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 |
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#define | STM32_CAN_USE_CAN1 FALSE |
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#define | STM32_CAN_USE_CAN2 FALSE |
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#define | STM32_CAN_CAN1_IRQ_PRIORITY 11 |
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#define | STM32_CAN_CAN2_IRQ_PRIORITY 11 |
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#define | STM32_EXT_EXTI0_IRQ_PRIORITY 6 |
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#define | STM32_EXT_EXTI1_IRQ_PRIORITY 6 |
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#define | STM32_EXT_EXTI2_IRQ_PRIORITY 6 |
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#define | STM32_EXT_EXTI3_IRQ_PRIORITY 6 |
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#define | STM32_EXT_EXTI4_IRQ_PRIORITY 6 |
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#define | STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 |
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#define | STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 |
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#define | STM32_EXT_EXTI16_IRQ_PRIORITY 6 |
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#define | STM32_EXT_EXTI17_IRQ_PRIORITY 15 |
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#define | STM32_EXT_EXTI18_IRQ_PRIORITY 6 |
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#define | STM32_EXT_EXTI19_IRQ_PRIORITY 6 |
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#define | STM32_EXT_EXTI20_IRQ_PRIORITY 6 |
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#define | STM32_EXT_EXTI21_IRQ_PRIORITY 15 |
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#define | STM32_EXT_EXTI22_IRQ_PRIORITY 15 |
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#define | STM32_GPT_USE_TIM1 FALSE |
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#define | STM32_GPT_USE_TIM2 FALSE |
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#define | STM32_GPT_USE_TIM3 FALSE |
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#define | STM32_GPT_USE_TIM4 FALSE |
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#define | STM32_GPT_USE_TIM5 FALSE |
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#define | STM32_GPT_USE_TIM6 FALSE |
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#define | STM32_GPT_USE_TIM7 FALSE |
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#define | STM32_GPT_USE_TIM8 FALSE |
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#define | STM32_GPT_USE_TIM9 FALSE |
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#define | STM32_GPT_USE_TIM11 FALSE |
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#define | STM32_GPT_USE_TIM12 FALSE |
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#define | STM32_GPT_USE_TIM14 FALSE |
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#define | STM32_GPT_TIM1_IRQ_PRIORITY 7 |
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#define | STM32_GPT_TIM2_IRQ_PRIORITY 7 |
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#define | STM32_GPT_TIM3_IRQ_PRIORITY 7 |
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#define | STM32_GPT_TIM4_IRQ_PRIORITY 7 |
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#define | STM32_GPT_TIM5_IRQ_PRIORITY 7 |
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#define | STM32_GPT_TIM6_IRQ_PRIORITY 7 |
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#define | STM32_GPT_TIM7_IRQ_PRIORITY 7 |
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#define | STM32_GPT_TIM8_IRQ_PRIORITY 7 |
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#define | STM32_GPT_TIM9_IRQ_PRIORITY 7 |
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#define | STM32_GPT_TIM11_IRQ_PRIORITY 7 |
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#define | STM32_GPT_TIM12_IRQ_PRIORITY 7 |
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#define | STM32_GPT_TIM14_IRQ_PRIORITY 7 |
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#define | STM32_I2C_USE_I2C1 FALSE |
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#define | STM32_I2C_USE_I2C2 FALSE |
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#define | STM32_I2C_USE_I2C3 FALSE |
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#define | STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) |
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#define | STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) |
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#define | STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) |
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#define | STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) |
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#define | STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) |
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#define | STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) |
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#define | STM32_I2C_I2C1_IRQ_PRIORITY 5 |
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#define | STM32_I2C_I2C2_IRQ_PRIORITY 5 |
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#define | STM32_I2C_I2C3_IRQ_PRIORITY 5 |
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#define | STM32_I2C_I2C1_DMA_PRIORITY 3 |
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#define | STM32_I2C_I2C2_DMA_PRIORITY 3 |
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#define | STM32_I2C_I2C3_DMA_PRIORITY 3 |
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#define | STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() |
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#define | STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() |
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#define | STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt() |
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#define | STM32_ICU_USE_TIM1 FALSE |
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#define | STM32_ICU_USE_TIM2 FALSE |
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#define | STM32_ICU_USE_TIM3 FALSE |
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#define | STM32_ICU_USE_TIM4 FALSE |
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#define | STM32_ICU_USE_TIM5 FALSE |
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#define | STM32_ICU_USE_TIM8 FALSE |
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#define | STM32_ICU_USE_TIM9 FALSE |
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#define | STM32_ICU_TIM1_IRQ_PRIORITY 7 |
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#define | STM32_ICU_TIM2_IRQ_PRIORITY 7 |
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#define | STM32_ICU_TIM3_IRQ_PRIORITY 7 |
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#define | STM32_ICU_TIM4_IRQ_PRIORITY 7 |
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#define | STM32_ICU_TIM5_IRQ_PRIORITY 7 |
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#define | STM32_ICU_TIM8_IRQ_PRIORITY 7 |
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#define | STM32_ICU_TIM9_IRQ_PRIORITY 7 |
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#define | STM32_MAC_TRANSMIT_BUFFERS 2 |
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#define | STM32_MAC_RECEIVE_BUFFERS 4 |
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#define | STM32_MAC_BUFFERS_SIZE 1522 |
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#define | STM32_MAC_PHY_TIMEOUT 100 |
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#define | STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE |
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#define | STM32_MAC_ETH1_IRQ_PRIORITY 13 |
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#define | STM32_MAC_IP_CHECKSUM_OFFLOAD 0 |
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#define | STM32_PWM_USE_ADVANCED FALSE |
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#define | STM32_PWM_USE_TIM1 FALSE |
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#define | STM32_PWM_USE_TIM2 FALSE |
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#define | STM32_PWM_USE_TIM3 FALSE |
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#define | STM32_PWM_USE_TIM4 FALSE |
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#define | STM32_PWM_USE_TIM5 FALSE |
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#define | STM32_PWM_USE_TIM8 FALSE |
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#define | STM32_PWM_USE_TIM9 FALSE |
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#define | STM32_PWM_TIM1_IRQ_PRIORITY 7 |
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#define | STM32_PWM_TIM2_IRQ_PRIORITY 7 |
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#define | STM32_PWM_TIM3_IRQ_PRIORITY 7 |
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#define | STM32_PWM_TIM4_IRQ_PRIORITY 7 |
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#define | STM32_PWM_TIM5_IRQ_PRIORITY 7 |
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#define | STM32_PWM_TIM8_IRQ_PRIORITY 7 |
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#define | STM32_PWM_TIM9_IRQ_PRIORITY 7 |
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#define | STM32_SERIAL_USE_USART1 FALSE |
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#define | STM32_SERIAL_USE_USART2 FALSE |
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#define | STM32_SERIAL_USE_USART3 FALSE |
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#define | STM32_SERIAL_USE_UART4 FALSE |
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#define | STM32_SERIAL_USE_UART5 FALSE |
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#define | STM32_SERIAL_USE_USART6 FALSE |
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#define | STM32_SERIAL_USART1_PRIORITY 12 |
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#define | STM32_SERIAL_USART2_PRIORITY 12 |
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#define | STM32_SERIAL_USART3_PRIORITY 12 |
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#define | STM32_SERIAL_UART4_PRIORITY 12 |
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#define | STM32_SERIAL_UART5_PRIORITY 12 |
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#define | STM32_SERIAL_USART6_PRIORITY 12 |
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#define | STM32_SPI_USE_SPI1 FALSE |
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#define | STM32_SPI_USE_SPI2 FALSE |
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#define | STM32_SPI_USE_SPI3 FALSE |
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#define | STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) |
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#define | STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) |
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#define | STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) |
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#define | STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) |
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#define | STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) |
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#define | STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) |
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#define | STM32_SPI_SPI1_DMA_PRIORITY 1 |
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#define | STM32_SPI_SPI2_DMA_PRIORITY 1 |
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#define | STM32_SPI_SPI3_DMA_PRIORITY 1 |
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#define | STM32_SPI_SPI1_IRQ_PRIORITY 10 |
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#define | STM32_SPI_SPI2_IRQ_PRIORITY 10 |
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#define | STM32_SPI_SPI3_IRQ_PRIORITY 10 |
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#define | STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() |
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#define | STM32_UART_USE_USART1 FALSE |
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#define | STM32_UART_USE_USART2 FALSE |
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#define | STM32_UART_USE_USART3 FALSE |
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#define | STM32_UART_USE_UART4 FALSE |
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#define | STM32_UART_USE_UART5 FALSE |
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#define | STM32_UART_USE_USART6 FALSE |
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#define | STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) |
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#define | STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) |
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#define | STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) |
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#define | STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) |
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#define | STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) |
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#define | STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) |
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#define | STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) |
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#define | STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) |
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#define | STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) |
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#define | STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) |
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#define | STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) |
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#define | STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) |
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#define | STM32_UART_USART1_IRQ_PRIORITY 12 |
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#define | STM32_UART_USART2_IRQ_PRIORITY 12 |
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#define | STM32_UART_USART3_IRQ_PRIORITY 12 |
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#define | STM32_UART_UART4_IRQ_PRIORITY 12 |
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#define | STM32_UART_UART5_IRQ_PRIORITY 12 |
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#define | STM32_UART_USART6_IRQ_PRIORITY 12 |
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#define | STM32_UART_USART1_DMA_PRIORITY 0 |
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#define | STM32_UART_USART2_DMA_PRIORITY 0 |
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#define | STM32_UART_USART3_DMA_PRIORITY 0 |
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#define | STM32_UART_UART4_DMA_PRIORITY 0 |
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#define | STM32_UART_UART5_DMA_PRIORITY 0 |
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#define | STM32_UART_USART6_DMA_PRIORITY 0 |
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#define | STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() |
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#define | STM32_USB_USE_OTG1 FALSE |
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#define | STM32_USB_USE_OTG2 FALSE |
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#define | STM32_USB_OTG1_IRQ_PRIORITY 14 |
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#define | STM32_USB_OTG2_IRQ_PRIORITY 14 |
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#define | STM32_USB_OTG1_RX_FIFO_SIZE 512 |
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#define | STM32_USB_OTG2_RX_FIFO_SIZE 1024 |
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#define | STM32_USB_OTG_THREAD_PRIO LOWPRIO |
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#define | STM32_USB_OTG_THREAD_STACK_SIZE 128 |
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#define | STM32_USB_OTGFIFO_FILL_BASEPRI 0 |
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#define | PIOS_INCLUDE_ANNUNC |
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#define | PIOS_INCLUDE_SPI |
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#define | PIOS_INCLUDE_SYS |
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#define | PIOS_INCLUDE_IAP |
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#define | PIOS_INCLUDE_USB |
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#define | PIOS_INCLUDE_USB_HID |
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#define | PIOS_INCLUDE_COM_MSG |
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#define | PIOS_INCLUDE_FLASH |
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#define | PIOS_INCLUDE_FLASH_INTERNAL |
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#define | PIOS_INCLUDE_FLASH_JEDEC |
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#define | DEBUG_PRINTF(level,...) |
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#define | BOARD_READABLE true |
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#define | BOARD_WRITABLE true |
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#define | MAX_DEL_RETRYS 3 |
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#define | PIOS_LED_HEARTBEAT 0 |
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#define | PIOS_LED_ALARM 1 |
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#define | PIOS_ANNUNCIATOR_BUZZER 2 |
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#define | PIOS_WATCHDOG_TIMEOUT 250 |
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#define | PIOS_WDG_REGISTER RTC_BKP_DR4 |
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#define | PIOS_COM_GPS (pios_com_gps_id) |
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#define | PIOS_COM_TELEM_USB (pios_com_telem_usb_id) |
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#define | PIOS_COM_BRIDGE (pios_com_bridge_id) |
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#define | PIOS_COM_VCP (pios_com_vcp_id) |
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#define | PIOS_COM_MAVLINK (pios_com_mavlink_id) |
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#define | PIOS_COM_HOTT (pios_com_hott_id) |
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#define | PIOS_COM_FRSKY_SENSOR_HUB (pios_com_frsky_sensor_hub_id) |
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#define | PIOS_COM_LIGHTTELEMETRY (pios_com_lighttelemetry_id) |
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#define | PIOS_COM_FRSKY_SPORT (pios_com_frsky_sport_id) |
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#define | PIOS_COM_OPENLOG (pios_com_openlog_logging_id) |
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#define | PIOS_COM_STORM32BGC (pios_com_storm32bgc_id) |
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#define | RS_ECC_NPARITY 4 |
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#define | PIOS_SYSCLK 168000000 |
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#define | PIOS_PERIPHERAL_APB1_CLOCK (PIOS_SYSCLK / 4) |
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#define | PIOS_PERIPHERAL_APB2_CLOCK (PIOS_SYSCLK / 2) |
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#define | PIOS_IRQ_PRIO_LOW 12 |
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#define | PIOS_IRQ_PRIO_MID 8 |
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#define | PIOS_IRQ_PRIO_HIGH 5 |
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#define | PIOS_IRQ_PRIO_HIGHEST 4 |
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#define | PIOS_RCVR_MAX_CHANNELS 12 |
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#define | PIOS_PPM_NUM_INPUTS 12 |
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#define | PIOS_PWM_NUM_INPUTS 8 |
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#define | PIOS_SPEKTRUM_NUM_INPUTS 12 |
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#define | PIOS_SBUS_NUM_INPUTS (16+2) |
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#define | PIOS_DSM_NUM_INPUTS 12 |
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#define | PIOS_HSUM_MAX_DEVS 2 |
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#define | PIOS_HSUM_NUM_INPUTS 32 |
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#define | PIOS_SERVO_UPDATE_HZ 50 |
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#define | PIOS_SERVOS_INITIAL_POSITION 0 /* dont want to start motors, have no pulse till settings loaded */ |
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#define | PIOS_TIM_MAX_DEVS 6 |
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#define | PIOS_ADC_MAX_OVERSAMPLING 2 |
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#define | VREF_PLUS 3.3 |
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#define | PIOS_USB_ENABLED 1 /* Should remove all references to this */ |
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#define | STABILIZATION_LQG |
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#define | PIOS_INCLUDE_FLASH_JEDEC |
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#define | PIOS_INCLUDE_I2C |
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#define | PIOS_INCLUDE_SPI |
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#define | PIOS_INCLUDE_FASTHEAP |
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#define | PIOS_INCLUDE_WS2811 |
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#define | PIOS_INCLUDE_OPENLRS |
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#define | PIOS_INCLUDE_OPENLRS_RCVR |
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#define | PIOS_INCLUDE_MAX7456 |
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#define | PIOS_INCLUDE_BMP280 |
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#define | PIOS_INCLUDE_BMP280_SPI |
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#define | PIOS_INCLUDE_HMC5883 |
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#define | PIOS_INCLUDE_HMC5983_I2C |
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#define | PIOS_INCLUDE_MPU |
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#define | PIOS_INCLUDE_MS5611 |
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#define | PIOS_INCLUDE_MPXV5004 |
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#define | PIOS_INCLUDE_MPXV7002 |
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#define | PIOS_TOLERATE_MISSING_SENSORS |
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#define | PIOS_INCLUDE_MAVLINK |
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#define | PIOS_INCLUDE_LIGHTTELEMETRY |
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#define | PIOS_INCLUDE_PWM |
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#define | SYSTEMMOD_RGBLED_SUPPORT |
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#define | CAMERASTAB_POI_MODE |
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#define | IDLE_COUNTS_PER_SEC_AT_NO_LOAD (9870518) |
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#define | PIOS_INCLUDE_LOG_TO_FLASH |
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#define | PIOS_LOGFLASH_SECT_SIZE 0x10000 /* 64kb */ |
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