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#define | BMX055_REG_ACC_CHIPID 0x00 |
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#define | BMX055_VAL_ACC_CHIPID 0xfa |
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#define | BMX055_REG_ACC_X_LSB 0x02 |
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#define | BMX055_REG_ACC_X_MSB 0x03 |
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#define | BMX055_REG_ACC_Y_LSB 0x04 |
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#define | BMX055_REG_ACC_Y_MSB 0x05 |
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#define | BMX055_REG_ACC_Z_LSB 0x06 |
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#define | BMX055_REG_ACC_Z_MSB 0x07 |
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#define | BMX055_REG_ACC_TEMP 0x08 |
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#define | BMX055_ACC_TEMP_OFFSET 23 |
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#define | BMX055_REG_ACC_INT_STATUS_0 0x09 |
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#define | BMX055_REG_ACC_INT_STATUS_1 0x0a |
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#define | BMX055_REG_ACC_INT_STATUS_2 0x0b |
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#define | BMX055_REG_ACC_INT_STATUS_3 0x0c |
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#define | BMX055_REG_ACC_FIFO_STATUS 0x0e |
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#define | BMX055_REG_ACC_PMU_RANGE 0x0f |
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#define | BMX055_VAL_ACC_PMU_RANGE_2G 0x03 |
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#define | BMX055_VAL_ACC_PMU_RANGE_4G 0x05 |
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#define | BMX055_VAL_ACC_PMU_RANGE_8G 0x08 |
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#define | BMX055_VAL_ACC_PMU_RANGE_16G 0x0c |
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#define | BMX055_REG_ACC_PMU_BW 0x10 |
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#define | BMX055_VAL_ACC_PMU_BW_7HZ81 0x08 |
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#define | BMX055_VAL_ACC_PMU_BW_15HZ63 0x09 |
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#define | BMX055_VAL_ACC_PMU_BW_31HZ25 0x0a |
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#define | BMX055_VAL_ACC_PMU_BW_62HZ5 0x0b |
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#define | BMX055_VAL_ACC_PMU_BW_125HZ 0x0c |
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#define | BMX055_VAL_ACC_PMU_BW_250HZ 0x0d |
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#define | BMX055_VAL_ACC_PMU_BW_500HZ 0x0e |
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#define | BMX055_VAL_ACC_PMU_BW_1KHZ 0x0f |
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#define | BMX055_REG_ACC_PMU_LPW 0x11 |
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#define | BMX055_VAL_ACC_PMU_LPW_NORMAL 0x00 |
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#define | BMX055_REG_ACC_PMU_LOW_POWER 0x12 |
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#define | BMX055_REG_ACC_ACCD_HBW 0x13 |
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#define | BMX055_VAL_ACC_ACCD_HBW_NORMAL 0x00 /* filtered data, shadowed */ |
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#define | BMX055_REG_ACC_BGW_SOFTRESET 0x14 |
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#define | BMX055_VAL_ACC_BGW_SOFTRESET_REQ 0xb6 /* value to trigger a reset */ |
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#define | BMX055_REG_ACC_INT_EN_0 0x16 |
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#define | BMX055_REG_ACC_INT_EN_1 0x17 |
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#define | BMX055_REG_ACC_INT_EN_2 0x18 |
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#define | BMX055_REG_ACC_INT_MAP_0 0x19 |
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#define | BMX055_REG_ACC_INT_MAP_1 0x1a |
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#define | BMX055_REG_ACC_INT_MAP_2 0x1b |
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#define | BMX055_REG_ACC_INT_SRC 0x1e |
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#define | BMX055_REG_ACC_INT_OUT_CTRL 0x20 |
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#define | BMX055_REG_ACC_INT_RST_LATCH 0x21 |
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#define | BMX055_REG_ACC_INT_0 0x22 |
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#define | BMX055_REG_ACC_INT_1 0x23 |
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#define | BMX055_REG_ACC_INT_2 0x24 |
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#define | BMX055_REG_ACC_INT_3 0x25 |
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#define | BMX055_REG_ACC_INT_4 0x26 |
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#define | BMX055_REG_ACC_INT_5 0x27 |
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#define | BMX055_REG_ACC_INT_6 0x28 |
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#define | BMX055_REG_ACC_INT_7 0x29 |
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#define | BMX055_REG_ACC_INT_8 0x2a |
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#define | BMX055_REG_ACC_INT_9 0x2b |
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#define | BMX055_REG_ACC_INT_A 0x2c |
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#define | BMX055_REG_ACC_INT_B 0x2d |
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#define | BMX055_REG_ACC_INT_C 0x2e |
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#define | BMX055_REG_ACC_INT_D 0x2f |
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#define | BMX055_REG_ACC_FIFO_CONFIG_0 0x30 |
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#define | BMX055_REG_ACC_PMU_SELF_TEST 0x32 |
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#define | BMX055_REG_ACC_TRIM_NVM_CTRL 0x33 |
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#define | BMX055_REG_ACC_BGW_SPI3_WDT 0x34 |
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#define | BMX055_REG_ACC_OFC_CTRL 0x36 |
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#define | BMX055_REG_ACC_OFC_SETTING 0x37 |
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#define | BMX055_REG_ACC_OFC_OFFSET_X 0x38 |
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#define | BMX055_REG_ACC_OFC_OFFSET_Y 0x39 |
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#define | BMX055_REG_ACC_OFC_OFFSET_Z 0x3a |
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#define | BMX055_REG_ACC_TRIM_GP0 0x3b |
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#define | BMX055_REG_ACC_TRIM_GP1 0x3c |
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#define | BMX055_REG_ACC_FIFO_CONFIG_1 0x3e |
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#define | BMX055_VAL_ACC_FIFO_CONFIG_1_BYPASS 0x00 |
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#define | BMX055_REG_ACC_FIFO_DATA 0x3f |
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#define | BMX055_REG_GYRO_CHIPID 0x00 |
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#define | BMX055_VAL_GYRO_CHIPID 0x0f |
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#define | BMX055_REG_GYRO_X_LSB 0x02 |
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#define | BMX055_REG_GYRO_X_MSB 0x03 |
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#define | BMX055_REG_GYRO_Y_LSB 0x04 |
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#define | BMX055_REG_GYRO_Y_MSB 0x05 |
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#define | BMX055_REG_GYRO_Z_LSB 0x06 |
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#define | BMX055_REG_GYRO_Z_MSB 0x07 |
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#define | BMX055_REG_GYRO_INT_STATUS_0 0x09 |
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#define | BMX055_REG_GYRO_INT_STATUS_1 0x0A |
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#define | BMX055_REG_GYRO_INT_STATUS_2 0x0B |
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#define | BMX055_REG_GYRO_INT_STATUS_3 0x0C |
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#define | BMX055_REG_GYRO_FIFO_STATUS 0x0E |
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#define | BMX055_REG_GYRO_RANGE 0x0F |
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#define | BMX055_VAL_GYRO_RANGE_2000DPS 0x00 |
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#define | BMX055_VAL_GYRO_RANGE_1000DPS 0x01 |
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#define | BMX055_VAL_GYRO_RANGE_500DPS 0x02 |
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#define | BMX055_VAL_GYRO_RANGE_250DPS 0x03 |
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#define | BMX055_VAL_GYRO_RANGE_125DPS 0x04 |
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#define | BMX055_REG_GYRO_BW 0x10 |
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#define | BMX055_VAL_GYRO_BW_47HZ 0x03 /* 400Hz ODR */ |
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#define | BMX055_VAL_GYRO_BW_116HZ 0x02 /* 1KHz ODR */ |
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#define | BMX055_VAL_GYRO_BW_230HZ 0x01 /* 2KHz ODR */ |
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#define | BMX055_VAL_GYRO_BW_UNFILT 0x00 /* 2KHz ODR */ |
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#define | BMX055_REG_GYRO_LPM1 0x11 |
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#define | BMX055_REG_GYRO_LPM2 0x12 |
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#define | BMX055_REG_GYRO_RATE_HBW 0x13 |
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#define | BMX055_REG_GYRO_BGW_SOFTRESET 0x14 |
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#define | BMX055_VAL_GYRO_BGW_SOFTRESET_REQ 0xb6 /* Takes 30ms! Typical! */ |
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#define | BMX055_REG_GYRO_INT_EN_0 0x15 |
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#define | BMX055_REG_GYRO_INT_EN_1 0x16 |
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#define | BMX055_REG_GYRO_INT_MAP_0 0x17 |
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#define | BMX055_REG_GYRO_INT_MAP_1 0x18 |
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#define | BMX055_REG_GYRO_INT_MAP_2 0x19 |
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#define | BMX055_REG_GYRO_INTERRUPTS_SELECTABLE_DATA_SOURCE 0x1A |
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#define | BMX055_REG_GYRO_FAST_OFFSET_COMPENSATION_MOTION_THRESHOLD 0x1B |
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#define | BMX055_REG_GYRO_MOTION_INT 0x1C |
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#define | BMX055_REG_GYRO_FIFO_WM_INT 0x1E |
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#define | BMX055_REG_GYRO_INT_RST_LATCH 0x21 |
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#define | BMX055_REG_GYRO_HIGH_TH_X 0x22 |
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#define | BMX055_REG_GYRO_HIGH_DUR_X 0x23 |
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#define | BMX055_REG_GYRO_HIGH_TH_Y 0x24 |
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#define | BMX055_REG_GYRO_HIGH_DUR_Y 0x25 |
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#define | BMX055_REG_GYRO_HIGH_TH_Z 0x26 |
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#define | BMX055_REG_GYRO_HIGH_DUR_Z 0x27 |
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#define | BMX055_REG_GYRO_SOC 0x31 |
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#define | BMX055_REG_GYRO_A_FOC 0x32 |
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#define | BMX055_REG_GYRO_TRIM_NVM_CTRL 0x33 |
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#define | BMX055_REG_GYRO_BGW_SPI3_WDT 0x34 |
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#define | BMX055_REG_GYRO_OFC1 0x36 |
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#define | BMX055_REG_GYRO_OFC2 0x37 |
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#define | BMX055_REG_GYRO_OFC3 0x38 |
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#define | BMX055_REG_GYRO_OFC4 0x39 |
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#define | BMX055_REG_GYRO_TRIM_GP0 0x3A |
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#define | BMX055_REG_GYRO_TRIM_GP1 0x3B |
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#define | BMX055_REG_GYRO_BIST 0x3C |
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#define | BMX055_REG_GYRO_FIFO_CONFIG_0 0x3D |
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#define | BMX055_REG_GYRO_FIFO_CONFIG_1 0x3E |
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#define | BMX055_REG_GYRO_FIFO_DATA 0x3F |
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