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cmsis_system.c
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1 
122 #include "stm32f4xx.h"
123 
140 /************************* Miscellaneous Configuration ************************/
143 /* #define DATA_IN_ExtSRAM */
144 
147 /* #define VECT_TAB_SRAM */
148 #define VECT_TAB_OFFSET 0x00
150 /******************************************************************************/
151 
152 /************************* PLL Parameters *************************************/
153 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
154 #define PLL_M 8
155 #define PLL_N 336
157 /* SYSCLK = PLL_VCO / PLL_P */
158 #define PLL_P 2
160 /* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
161 #define PLL_Q 7
163 /******************************************************************************/
164 
181  uint32_t SystemCoreClock = 168000000;
183  __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
193 static void SetSysClock(void);
194 #ifdef DATA_IN_ExtSRAM
195  static void SystemInit_ExtMemCtl(void);
196 #endif /* DATA_IN_ExtSRAM */
197 
212 void SystemInit(void)
213 {
214  /* FPU settings ------------------------------------------------------------*/
215  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
216  SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
217  #endif
218  /* Reset the RCC clock configuration to the default reset state ------------*/
219  /* Set HSION bit */
220  RCC->CR |= (uint32_t)0x00000001;
221 
222  /* Reset CFGR register */
223  RCC->CFGR = 0x00000000;
224 
225  /* Reset HSEON, CSSON and PLLON bits */
226  RCC->CR &= (uint32_t)0xFEF6FFFF;
227 
228  /* Reset PLLCFGR register */
229  RCC->PLLCFGR = 0x24003010;
230 
231  /* Reset HSEBYP bit */
232  RCC->CR &= (uint32_t)0xFFFBFFFF;
233 
234  /* Disable all interrupts */
235  RCC->CIR = 0x00000000;
236 
237 #ifdef DATA_IN_ExtSRAM
238  SystemInit_ExtMemCtl();
239 #endif /* DATA_IN_ExtSRAM */
240 
241  /* Configure the System clock source, PLL Multiplier and Divider factors,
242  AHB/APBx prescalers and Flash settings ----------------------------------*/
243  SetSysClock();
244 
245  /* Configure the Vector Table location add offset address ------------------*/
246 #ifdef VECT_TAB_SRAM
247  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
248 #else
249  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
250 #endif
251 }
252 
288 void SystemCoreClockUpdate(void)
289 {
290  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
291 
292  /* Get SYSCLK source -------------------------------------------------------*/
293  tmp = RCC->CFGR & RCC_CFGR_SWS;
294 
295  switch (tmp)
296  {
297  case 0x00: /* HSI used as system clock source */
298  SystemCoreClock = HSI_VALUE;
299  break;
300  case 0x04: /* HSE used as system clock source */
301  SystemCoreClock = HSE_VALUE;
302  break;
303  case 0x08: /* PLL used as system clock source */
304 
305  /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
306  SYSCLK = PLL_VCO / PLL_P
307  */
308  pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
309  pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
310 
311  if (pllsource != 0)
312  {
313  /* HSE used as PLL clock source */
314  pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
315  }
316  else
317  {
318  /* HSI used as PLL clock source */
319  pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
320  }
321 
322  pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
323  SystemCoreClock = pllvco/pllp;
324  break;
325  default:
326  SystemCoreClock = HSI_VALUE;
327  break;
328  }
329  /* Compute HCLK frequency --------------------------------------------------*/
330  /* Get HCLK prescaler */
331  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
332  /* HCLK frequency */
333  SystemCoreClock >>= tmp;
334 }
335 
343 static void SetSysClock(void)
344 {
345 /******************************************************************************/
346 /* PLL (clocked by HSE) used as System clock source */
347 /******************************************************************************/
348  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
349 
350  /* Enable HSE */
351  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
352 
353  /* Wait till HSE is ready and if Time out is reached exit */
354  do
355  {
356  HSEStatus = RCC->CR & RCC_CR_HSERDY;
357  StartUpCounter++;
358  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
359 
360  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
361  {
362  HSEStatus = (uint32_t)0x01;
363  }
364  else
365  {
366  HSEStatus = (uint32_t)0x00;
367  }
368 
369  if (HSEStatus == (uint32_t)0x01)
370  {
371  /* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */
372  RCC->APB1ENR |= RCC_APB1ENR_PWREN;
373  PWR->CR |= PWR_CR_VOS;
374 
375  /* HCLK = SYSCLK / 1*/
376  RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
377 
378  /* PCLK2 = HCLK / 2*/
379  RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
380 
381  /* PCLK1 = HCLK / 4*/
382  RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
383 
384  /* Configure the main PLL */
385  RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
386  (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
387 
388  /* Enable the main PLL */
389  RCC->CR |= RCC_CR_PLLON;
390 
391  /* Wait till the main PLL is ready */
392  while((RCC->CR & RCC_CR_PLLRDY) == 0);
393 
394  /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
395  FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
396 
397  /* Select the main PLL as system clock source */
398  RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
399  RCC->CFGR |= RCC_CFGR_SW_PLL;
400 
401  /* Wait till the main PLL is used as system clock source */
402  while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
403  }
404  else
405  { /* If HSE fails to start-up, the application will have wrong clock
406  configuration. User can add here some code to deal with this error */
407  }
408 
409 }
410 
416 #ifdef DATA_IN_ExtSRAM
417 
424 void SystemInit_ExtMemCtl(void)
425 {
426 /*-- GPIOs Configuration -----------------------------------------------------*/
427 /*
428  +-------------------+--------------------+------------------+------------------+
429  + SRAM pins assignment +
430  +-------------------+--------------------+------------------+------------------+
431  | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
432  | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
433  | PD4 <-> FSMC_NOE | PE3 <-> FSMC_A19 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
434  | PD5 <-> FSMC_NWE | PE4 <-> FSMC_A20 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
435  | PD8 <-> FSMC_D13 | PE7 <-> FSMC_D4 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
436  | PD9 <-> FSMC_D14 | PE8 <-> FSMC_D5 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
437  | PD10 <-> FSMC_D15 | PE9 <-> FSMC_D6 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
438  | PD11 <-> FSMC_A16 | PE10 <-> FSMC_D7 | PF13 <-> FSMC_A7 |------------------+
439  | PD12 <-> FSMC_A17 | PE11 <-> FSMC_D8 | PF14 <-> FSMC_A8 |
440  | PD13 <-> FSMC_A18 | PE12 <-> FSMC_D9 | PF15 <-> FSMC_A9 |
441  | PD14 <-> FSMC_D0 | PE13 <-> FSMC_D10 |------------------+
442  | PD15 <-> FSMC_D1 | PE14 <-> FSMC_D11 |
443  | | PE15 <-> FSMC_D12 |
444  +-------------------+--------------------+
445 */
446  /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
447  RCC->AHB1ENR = 0x00000078;
448 
449  /* Connect PDx pins to FSMC Alternate function */
450  GPIOD->AFR[0] = 0x00cc00cc;
451  GPIOD->AFR[1] = 0xcc0ccccc;
452  /* Configure PDx pins in Alternate function mode */
453  GPIOD->MODER = 0xaaaa0a0a;
454  /* Configure PDx pins speed to 100 MHz */
455  GPIOD->OSPEEDR = 0xffff0f0f;
456  /* Configure PDx pins Output type to push-pull */
457  GPIOD->OTYPER = 0x00000000;
458  /* No pull-up, pull-down for PDx pins */
459  GPIOD->PUPDR = 0x00000000;
460 
461  /* Connect PEx pins to FSMC Alternate function */
462  GPIOE->AFR[0] = 0xc00cc0cc;
463  GPIOE->AFR[1] = 0xcccccccc;
464  /* Configure PEx pins in Alternate function mode */
465  GPIOE->MODER = 0xaaaa828a;
466  /* Configure PEx pins speed to 100 MHz */
467  GPIOE->OSPEEDR = 0xffffc3cf;
468  /* Configure PEx pins Output type to push-pull */
469  GPIOE->OTYPER = 0x00000000;
470  /* No pull-up, pull-down for PEx pins */
471  GPIOE->PUPDR = 0x00000000;
472 
473  /* Connect PFx pins to FSMC Alternate function */
474  GPIOF->AFR[0] = 0x00cccccc;
475  GPIOF->AFR[1] = 0xcccc0000;
476  /* Configure PFx pins in Alternate function mode */
477  GPIOF->MODER = 0xaa000aaa;
478  /* Configure PFx pins speed to 100 MHz */
479  GPIOF->OSPEEDR = 0xff000fff;
480  /* Configure PFx pins Output type to push-pull */
481  GPIOF->OTYPER = 0x00000000;
482  /* No pull-up, pull-down for PFx pins */
483  GPIOF->PUPDR = 0x00000000;
484 
485  /* Connect PGx pins to FSMC Alternate function */
486  GPIOG->AFR[0] = 0x00cccccc;
487  GPIOG->AFR[1] = 0x000000c0;
488  /* Configure PGx pins in Alternate function mode */
489  GPIOG->MODER = 0x00080aaa;
490  /* Configure PGx pins speed to 100 MHz */
491  GPIOG->OSPEEDR = 0x000c0fff;
492  /* Configure PGx pins Output type to push-pull */
493  GPIOG->OTYPER = 0x00000000;
494  /* No pull-up, pull-down for PGx pins */
495  GPIOG->PUPDR = 0x00000000;
496 
497 /*-- FSMC Configuration ------------------------------------------------------*/
498  /* Enable the FSMC interface clock */
499  RCC->AHB3ENR = 0x00000001;
500 
501  /* Configure and enable Bank1_SRAM2 */
502  FSMC_Bank1->BTCR[2] = 0x00001015;
503  FSMC_Bank1->BTCR[3] = 0x00010603;
504  FSMC_Bank1E->BWTR[2] = 0x0fffffff;
505  /*
506  Bank1_SRAM2 is configured as follow:
507 
508  p.FSMC_AddressSetupTime = 3;
509  p.FSMC_AddressHoldTime = 0;
510  p.FSMC_DataSetupTime = 6;
511  p.FSMC_BusTurnAroundDuration = 1;
512  p.FSMC_CLKDivision = 0;
513  p.FSMC_DataLatency = 0;
514  p.FSMC_AccessMode = FSMC_AccessMode_A;
515 
516  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
517  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
518  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;
519  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
520  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
521  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
522  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
523  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
524  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
525  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
526  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
527  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
528  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
529  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
530  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
531 */
532 }
533 #endif /* DATA_IN_ExtSRAM */
534 
535 
553 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
554 
static void SetSysClock(void)
Configures the System clock source, PLL Multiplier and Divider factors, AHB/APBx prescalers and Flash...
Definition: cmsis_system.c:344
void SystemCoreClockUpdate(void)
Update SystemCoreClock variable according to Clock Register Values. The SystemCoreClock variable cont...
Definition: cmsis_system.c:289
void SystemInit(void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the Syst...
Definition: cmsis_system.c:213
#define PLL_Q
Definition: cmsis_system.c:162
#define PLL_M
Definition: cmsis_system.c:155
__I uint8_t AHBPrescTable[16]
Definition: cmsis_system.c:184
#define VECT_TAB_OFFSET
Definition: cmsis_system.c:148
uint32_t SystemCoreClock
Definition: cmsis_system.c:182